Journal Paper

  1. 1. M. Hua, X. Cai, S. Yang, Z. Zhang, Z. Zheng, N. Wang, and K. J. Chen, ‘Enhanced Gate Reliability in GaN MIS-FETs by Converting the GaN channel into Crystalline Gallium Oxynitride’, ACS Applied Elec. Material, Apr. 2019.
  2. 2. X. Cai*, M. Hua*, Z. Zhang, S. Yang, Z. Zheng, Y. Cai, K. J. Chen, and N. Wang, ‘Atomic-scale identification of crystalline GaON nanophase for enhanced GaN MIS-FET channel’, Applied Physics Letters, vol. 114, no. 5, p. 053109, Feb. 2019. (equal-contribution first author)
  3. 3. M. Hua, J. Wei, Q. Bao, Z. Zheng, Z. Zhang, J. He, and K. J. Chen, ‘Hole-Induced Threshold Voltage Shift Under Reverse-Bias Stress in E-Mode GaN MIS-FET’, IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3831–3838, Sep. 2018.
  4. 4. M. Hua, J. Wei, Q. Bao, Z. Zhang, Z. Zheng, and K. J. Chen, "Dependence of VTH Stability on Gate-Bias under Reverse-Bias Stress in E-mode GaN MIS-FET," IEEE Elec. Dev. Lett., vol. 39, no. 3, pp. 413–416, Jan. 2018.
  5. 5. K. Kim*, M. Hua*, D. Liu, J. Kim, K. J. Chen, and Z. Ma, "Efficiency enhancement of InGaN/GaN blue light-emitting diodes with top surface deposition of AlN/Al2O3," Nano Energy, vol. 43, pp. 259–269, Jan. 2018. (equal-contribution first author)
  6. 6. M. Hua, Q. Qian, J. Wei, Z. Zhang, G. Tang, and K. J. Chen, "Bias Temperature Instability of Normally-off GaN MIS-FET with Low-Pressure Chemical Vapor Deposition SiNx Gate Dielectric," Phys. Status Solidi A., DOI: 10.1002/pssa.201700641, Jan. 2018.
  7. 7. M. Hua, J. Wei, G. Tang, Z. Zhang, X. Cai, N. Wang, and K. J. Chen, "Normally-off LPCVD-SiNx/GaN MIS-FET with Crystalline Oxidation Interlayer," IEEE Elec. Dev. Lett., vol. 38, no. 7, pp. 929–932, Jul. 2017.
  8. 8. M. Hua, Y. Lu, S. Liu, C. Liu, K. Fu, Y. Cai, B. Zhang, and K. J. Chen, "Compatibility of AlN/SiNx Passivation With LPCVD-SiNx Gate Dielectric in GaN-Based MIS-HEMT," IEEE Elec. Dev. Lett., vol. 37, No. 3, pp. 265-268, 2016.
  9. 9. M. Hua, C. Liu, S. Yang, S. Liu, K. Fu, Z. Dong, Y. Cai, B. Zhang, and K. J. Chen, "Characterization of Leakage and Reliability of SiNx Gate Dielectric by Low-Pressure Chemical Vapor Deposition for GaN-based MIS-HEMTs, " IEEE Trans. Electron Devices, vol. 62, No. 10, pp. 3215-3222, 2015.
  10. 10. M. Hua, C. Liu, S. Yang, S. Liu, K. Fu, Z. Dong, Y. Cai, B. Zhang, and K. J. Chen, " GaN-Based Metal-Insulator-Semiconductor High-Electron-Mobility Transistors Using Low Pressure Chemical Vapor Deposition Silicon Nitride (LPCVD-SiNx) as Gate Dielectric," IEEE Elec. Dev. Lett., vol. 36, No. 5, pp. 448-450, 2015.
  11. 11. J. Lei, J. Wei, G. Tang, Z. Zhang, M. Hua, Z. Zheng, and K. J. Chen, ‘Reverse-Conducting Normally-OFF Double-Channel AlGaN/GaN Power Transistor with Interdigital Built-In Schottky Barrier Diode’, IEEE Transactions on Electron Devices, 2019.
  12. 12. J. Wei, R. Xie, H. Xu, H. Wang, Y. Wang, M. Hua, K. Zhong, G. Tang, J. He, M. Zhang, and K. J. Chen, ‘Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in p-GaN Gate HEMTs’, IEEE Electron Device Letters, 2019.
  13. 13. X. Lin, Y. Zhu, Y. Qi, G. Zhou, W. Li, Y. Jiang, J. Zhang, R. Sokolovskj, Y. Jiang, M. Hua, Hongyu Yuet al., ‘Achieving sub-1 Ohm-mm Non-Recess S/D Contact Resistance in GaN HEMTs Utilizing Simple CMOS Compatible La/Ti/Al/Ti Metal Contacts’, arXiv preprint arXiv:1902.00227, 2019.
  14. 14. Z. Zhang, M. Hua, J. He, G. Tang, Q. Qian, and K. J. Chen, ‘Ab initio study of impact of nitridation at amorphous-SiNx/GaN interface’, Appl. Phys. Express, vol. 11, no. 8, p. 081003, Jul. 2018.
  15. 15. J. Lei, J. Wei, G. Tang, Z. Zhang, Q. Qian, Z. Zheng, M. Hua, and Kevin J. Chen, “Reverse-Blocking Normally-Off GaN Double-Channel MOS-HEMT with Low Reverse Leakage Current and Low ON-State Resistance,” IEEE Electron Device Lett., vol.39, No.7, pp.1003-1006, 2018.
  16. 16. H. Amano, Y. Baines, E. Beam, M. Borga, T. Bouchet, P. Chalker,…M. Hua, … and Y. Zhang, “The 2018 GaN Power Electronics Roadmap,” Joutnal of Physics D: Applied Physics, vol. 51, no. 16, pp. 1, Mar. 2018.
  17. 17. J. Lei, J Wei, G Tang, Z Zhang, Q Qian, Z Zheng, M Hua, K. J. Chen, ‘650-V Double-Channel Lateral Schottky Barrier Diode With Dual-Recess Gated Anode’, IEEE Electron Device Letters, vol. 39, no. 2, pp. 260–263, Feb. 2018.
  18. 18. G. Tang, J. Wei, Z. Zhang, X. Tang, M. Hua, H. Wang, and K. J. Chen, “Dynamic RON of GaN-on-Si Lateral Power Devices with a Floating Substrate Termination,” IEEE Electron Device Lett., vol. 38, no. 7, pp. 937–940, Jul. 2017.
  19. 19. Z. Zhang, B. Li, Q. Qian, X. Tang, M. Hua, B. Huang, and K. J. Chen, “Revealing the Nitridation Effects on GaN Surface by First-Principles Calculation and X-Ray/Ultraviolet Photoemission Spectroscopy,” IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 4036–4043, Oct. 2017.
  20. 20. Q. Qian, Z. Zhang, M. Hua, J. Wei, J. Lei, and K. J. Chen, ‘Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET’, Applied Physics Express, vol. 10, no. 12, p. 125201, 2017.
  21. 21. Q. Qian, Z. Zhang, M. Hua, G. Tang, J. Lei, F. Lan, Y. Xu, R. Yan, and K. J. Chen, "Enhanced dielectric deposition on single-layer MoS2 with low damage using remote N2 plasma treatment," Nanotechnology, vol. 28, No. 17, p. 175202, 2017.
  22. 22. Q. Qian, B. Li, M. Hua, Z. Zhang, F. Lan, Y. Xu, R. Yan, and K. J. Chen, "Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer," Scientific Reports, vol. 6, p. 27676, 2016.
  23. 23. K. J. Chen, S. Yang, S. Liu, C. Liu, and M. Hua, "Toward reliable MIS- and MOS-gate structures for GaN lateral power devices," Phys. Status Solidi A, vol. 213, pp. 861-867, 2016.
  24. 24. S. Huang, S. Tang, Z. Tang, M. Hua, X. Wang, K. Wei, Q. Bao, X. Liu, and K. J. Chen, “Device physics towards high performance GaN-based power electronics,” Sci. Sin. Phys. Mech. Astron., vol. 46, no. 10, 2016.
  25. 25. S. Yang, S. Liu, C. Liu, M. Hua, and K. J. Chen, “Gate Stack Engineering for GaN Lateral Power Transistors, " Semicond. Sci. Technol., 31, 024001, 2016.
  26. 26. J. Wei, S. Liu, B. Li, X. Tang, Y. Lu, C. Liu, M. Hua, Z. Zhang, G. Tang, and K. J. Chen, "Low On-Resistance Normally-Off GaN Double-Channel Metal–Oxide–Semiconductor High-Electron-Mobility Transistor, " IEEE Elec. Dev. Lett., vol. 36, No. 12, pp. 1287-1290, 2015.
  27. 27. S. Huang, X. Liu, K. Wei, G. Liu, X. Wang, B. Sun, X. Yang, B. Shen, C. Liu, S. Liu, M. Hua, S. Yang, and K. J. Chen, "O3-sourced atomic layer deposition of high quality Al2O3 gate dielectric for normally-off GaN metal-insulator-semiconductor high-electron-mobility transistors, " Appl. Phys. Lett., 106(3), 033507, 2015.


Conference paper

  1. 1. M. Hua, S. Yang, Z. Zheng, J. Wei, Z. Zhang, and K. J. Chen, " Effects of Substrate Termination on Reverse-Bias Stress Reliability of Normally-Off Lateral GaN-on-Si MIS-FETs," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  2. 2. M. Hua, X. Cai, S. Yang, Z. Zhang, Z. Zheng, J. Wei, N. Wang, and K. J. Chen, ‘Suppressed Hole-Induced Degradation in E-mode GaN MIS-FETs with Crystalline GaOxN1-x Channel’, in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 30.3.1-30.3.4.
  3. 3. M. Hua and K. J. Chen, ‘High-performance Enhancement-mode GaN Power MIS-FET with Interface Protection Layer’, in 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018, pp. 1–5. (invited talk)
  4. 4. M. Hua, and Kevin J. Chen, "Reliability and Stability of Normally-off GaN Power MIS-FETs with LPCVD-SiNx Gate Dielectric," 14th International Conference on Solid State and Integrated Circuit Technology, Qingdao, China, Oct. 31-Nov. 03, 2018. (invited talk)
  5. 5. Kevin J. Chen, M. Hua, Z. Zhang, and J. He, "Enhancement-mode GaN-based MIS-FETs and MIS-HEMTs", MRS Spring Meeting & Exhibit, Phoenix, US, Apr. 02-06, 2018. (invited talk)
  6. 6. M. Hua, J. Wei, Q. Bao, Z. Zhang, J. He, Z. Zheng, J. Lei, and K. J. Chen, "Reverse-Bias Stability and Reliability of Hole-Barrier-Free E-mode LPCVD-SiNx/GaN MIS-FETs," 2017 Int. Electron Device Meeting (IEDM 2017), San Francisco, CA, USA, Dec. 2-6, 2017.
  7. 7. M. Hua, Q. Qian, J. Wei, Z. Zhang, G. Tang, and K. J. Chen, "PBTI and NBTI of Fully-recessed E-mode LPCVD-SiNx/GaN MIS-FETs with PECVD-SiNx Interfacial Protection Layer," 12th Int. Conf. on Nitride Semiconductors (ICNS-12), Strasbourg, France, July 24-28, 2017.
  8. 8. M. Hua, Z. Zhang, Q. Qian, J. Wei, Q. Bao, G. Tang, and K. J. Chen, "High-performance Fully-recessed Enhancement-mode GaN MIS-FETs with Crystalline Oxide Interlayer," 2017 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’17), Sapporo, Japan, May 28-June 1, 2017.
  9. 9. M. Hua, Y. Lu, S. Liu, C. Liu, K. Fu, Y. Cai, B. Zhang, and K. J. Chen, " TDDB and PBTI Characterizations of Fully-recessed E-mode GaN MIS-FETs with LPCVD-SiNx/PECVD-SiNx Gate Dielectric Stack," CS MANTECH Conference, Indian Wells, California, USA, May 22-25, 2017.
  10. 10. M. Hua, Z. Zhang, J. Wei, J. Lei, G. Tang, K. Fu, Y. Cai, B. Zhang, and K. J. Chen, "Integration of LPCVD-SiNx Gate Dielectric with Recessed-gate E-mode GaN MIS-FETs: Toward High Performance, High Stability and Long TDDB Lifetime," 2016 Int. Electron Device Meeting (IEDM 2016), San Francisco, CA, USA, Dec. 5-7, 2016.
  11. 11. M. Hua, Y. Lu, S. Liu, C. Liu, K. Fu, Y. Cai, B. Zhang, and K. J. Chen, "Compatibility of AlN/SiNx Passivation with High-Temperature Process," CS MANTECH Conference, Miami, Florida, USA, May 16-19, 2016.
  12. 12. M. Hua, C. Liu, S. Yang, S. Liu, K. Fu, Z. Dong, Y. Cai, B. Zhang, and K. J. Chen, "Gate Leakage and Time-Dependent Dielectric Breakdown Characteristics of LPCVD-SiNx/AlGaN/GaN MIS-HEMTs," 11th Int. Conf. on Nitride Semiconductors (ICNS-11), Beijing, China, Aug. 30- Sept. 4, 2015.
  13. 13. M. Hua, C. Liu, S. Yang, S. Liu, Y. Lu, K. Fu, Z. Dong, Y. Cai, B. Zhang, and K. J. Chen, "650-V GaN-Based MIS-HEMTs Using LPCVD-SiNx as Passivation and Gate Dielectric," 2015 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’15), Hong Kong, China, May 10-14, 2015.
  14. 14. J. Wei, H. Xu, R. Xie, M. Zhang, H. Wang, Y. Wang, K. Zhong, M. Hua, J. He, and K. J. Chen, " Dynamic Threshold Voltage in p-GaN Gate HEMT," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  15. 15. J. He, J. Wei, S. Yang, M. Hua, K. Zhong, and K. J. Chen, " Temperature-Dependent Gate Degradation of p-GaN Gate HEMTs Under Static and Dynamic Positive Gate Stress," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  16. 16. Z. Zheng, M. Hua, J. Wei, Z. Zhang, and K. J. Chen, " Identifying the Location of Hole-Induced Gate Degradation in LPCVD-SiNx/GaN Mis-Fets Under High Reverse-Bias Stress," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  17. 17. J. Lei, J. Wei, G. Tang, Z. Zhang, Q. Qian, M. Hua, Z. Zheng, Y. Wang, and K. J. Chen, " Charge-Modulated Schottky Barrier Lowering Effect in GaN Double-Channel Lateral Power SBDs with Gated Anode," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  18. 18. Y. Wang, J. Wei, S. Yang, J. Lei, M. Hua, and K. J. Chen, " Characterization of Dynamic IOFF in Schottky-Type p-GaN Gate HEMTs," 2019 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’19), Shanghai, China, May 19-23, 2019.
  19. 19. Z. Zhang, M. Hua, J. He, Q. Qian, and Kevin J. Chen, "Modification of amorphous-SiNx/GaN Interface Trap Density by Nitridation: A First-Principles Calculation Study," CS MANTECH Conference, Austin, Texas, USA, May 2018.
  20. 20. J. He, M. Hua, Z. Zhang, G. Tang, and K. J. Chen, "Performance and Stability of Enhancement-mode Fully-recessed GaN MIS-FETs and Partially-recessed MIS-HEMTs with PECVD-SiNx/LPCVD-SiNx Gate Dielectric," CS MANTECH Conference, Austin, Texas, USA, May 2018.
  21. 21. J. He, M. Hua, G. Tang, Z. Zhang and K. J. Chen, "Comparison of E-mode fully-recessed GaN MIS-FETs and partially-recessed MIS-HEMTs with PECVD-SiNx/LPCVD-SiNx gate stack," 12th Int. Conf. on Nitride Semiconductors (ICNS-12), Strasbourg, France, July 24-28, 2017.
  22. 22. J. Lei, J. Wei, G. Tang, Z. Zhang, Q. Qian, Z. Zheng, M. Hua, and K. J. Chen, "650-V Double-Channel Lateral Schottky Barrier Diode with Dual-Recess Gated Anode," 2017 Int. Electron Device Meeting (IEDM 2017), San Francisco, CA, USA, Dec. 2-6, 2017.
  23. 23. Q. Qian, Z. Zhang, M. Hua, J. Wei, J. Lei, and K. J. Chen, “Low-Resistance Contact to Single-Layer MoS2 by Depositing Ultrathin High-k Dielectric with Remote N2 Plasma Treatment as Tunneling Layer,” 2017 International Conference on Solid State Device and Materials (SSDM 2017), Sendai, Japan, Sep. 19-21, 2017.
  24. 24. G. Tang, J. Wei, Z. Zhang, X. Tang, M. Hua, H. Wang, and K. J. Chen, "Characterization and Analysis of Dynamic RON of GaN-on-Si Lateral Power Devices with Grounded and Floating Si Substrate,"12th Int. Conf. on Nitride Semiconductors (ICNS-12), Strasbourg, France, July 24-28, 2017.
  25. 25. G. Tang, J. Wei, Z. Zhang, X. Tang, M. Hua, H. Wang, and K. J. Chen, "Impact of Substrate Termination on Dynamic Performance of GaN-on-Si Lateral Power Devices," 2017 Int. Symp. On Power Semiconductor Devices and ICs (ISPSD’17), Sapporo, Japan, May 28-June 1, 2017.
  26. 26. Z. Zhang, B. Li, X. Tang, Q. Qian, M. Hua, B. Huang, and K. J. Chen, " First-Principles Study of GaN Surface Electronic Structures with Ga, O or N Adatom," 47th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, CA, USA, Dec. 8-10, 2016.
  27. 27. Z. Zhang, B. Li, X. Tang, Q. Qian, M. Hua, B. Huang, and K. J. Chen, "Nitridation of GaN Surface for Power Device Application: A First-Principles Study," 2016 Int. Electron Device Meeting (IEDM 2016), San Francisco, CA, USA, Dec. 5-7, 2016.
  28. 28. S. Yang, S. Liu, C. Liu, M. Hua, G. Longobardi, F. Udrea, and K. J. Chen, " Performance Enhancement and Characterization Techniques for GaN Power Devices," 2016 Compound Semiconductor Week (CSW 2016), Toyama, Japan, June 26-30, 2016.
  29. 29. J. Wei, S. Liu, B. Li, X. Tang, Y. Lu, C. Liu, M. Hua, Z. Zhang, G. Tang, and K. J. Chen, "Enhancement-mode GaN Double-Channel MOS-HEMT with Low On-resistance and Robust Gate Recess," 2015 Int. Electron Device Meeting (IEDM 2015), Washington, DC, USA, Dec. 7-9, 2015.


Patents Owned

  1. 1. Jing Chen, Mengyuan Hua, “Metal-insulator-semiconductor field-effect-transistors (MIS_FETs) with gate-dielectric/semiconductor interfacial protection layer”, U.S. Patent Application No. 62/494813, Aug. 22, 2016.